IEEE openSilicon
IEEE RF IC Series
Joint Flagship Initiative • Academic & Industry PatronsIEEE Bangalore Section
IEEE - Advancing Technology for Humanity
IEEE Bangalore Section
IEEE Sensors Council
IEEE openSilicon
Physical Silicon Tape-Out Track • Candidate Registration Live

Master RF IC Design for 5G/6G on Open-Source Silicon

An intensive 8-Module Masterclass bridging high-frequency architectural theory, zero-cost FOSS EDA pipelines, and open-source MPW shuttle tape-outs with industry-standard Open-Source PDKs (OS PDKs). Top validated designs qualify for physical silicon tape-out fabrication!

0Mod
Intensive Modules
0%
FOSS EDA Toolchain
0nm
Foundry Silicon PDKs
$0
License Barriers
Explore 8-Module Curriculum
Physical Silicon Architecture

From Schematic to Physical Silicon Tape-Out

Experience the complete semiconductor engineering lifecycle. Move past simulation theory into real-world Open-Source PDKs (OS PDKs) and automated MPW foundry manufacturing shuttles.

130nm Silicon

Foundry Open MPW Shuttles

Fabrication-ready flow targeting SkyWater 130nm CMOS and IHP 130nm BiCMOS open PDKs. Validated student team designs advance directly into physical silicon tape-out shuttles.

Explore Silicon Specs
$0 vs $150k

Zero-License FOSS Toolchain

Replace prohibitive enterprise EDA licenses ($150,000/seat/year) with production-grade open-source tools: Xschem, Ngspice, Qucs-S, and KLayout.

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Physical Verification

Real-Time DRC / LVS Sign-Off

Rigorous geometry Design Rule Checking (DRC) and Layout-Versus-Schematic (LVS) verification using Netgen and KLayout geometry engines.

View Verification Flow
Verifiable Badge

IEEE Dual-Tier Credentials & Tape-Out Track

Earn institutional recognition endorsed by IEEE Sensors Council RIT-B & IEEE Bangalore Section. Outstanding designs qualify for the Flagship Silicon Capstone Tape-Out Distinction.

Review Certification Tracks
Zero License Barriers

Proprietary vs. Open-Source Toolchain

Transitioning from prohibitive commercial enterprise licenses to production-grade FOSS EDA pipelines capable of tape-out on silicon foundries.

Commercial Equivalent: ~$150,000 / seat / yrSeries FOSS Toolchain: $0 (Completely Free & Reproducible)
Schematic Entry
Cadence Virtuoso Schematic Editor
FOSS Alternative:Xschem / Qucs-S
Role in Design Flow:Transistor-level RF schematic capture, port setup & hierarchical symbol generation
SPICE Simulation
Spectre RF / Keysight ADS
FOSS Alternative:Ngspice / Xyce
Role in Design Flow:High-frequency SPICE engine simulations (AC, DC, Transient, Periodic Steady-State / PSS)
RF Data Analytics
Keysight Data Display / MATLAB
FOSS Alternative:Python (scikit-rf + matplotlib)
Role in Design Flow:S-parameter Touchstone (.s2p) parsing, Stability circles, and Smith Chart impedance plots
3D EM Modeling
Ansys HFSS / Keysight Momentum
FOSS Alternative:openEMS (FDTD)
Role in Design Flow:3D Electromagnetic field solver for on-chip planar inductors, transformers & microstrips
Silicon Layout
Cadence Virtuoso Layout Suite
FOSS Alternative:KLayout / Magic VLSI
Role in Design Flow:Physical mask drawing, GDSII/OASIS generation, active device placement & guard rings
Physical Sign-off
Siemens Calibre (DRC/LVS)
FOSS Alternative:Netgen + KLayout Geometry DRC
Role in Design Flow:Full-chip Design Rule Checking (DRC) and Layout-Versus-Schematic (LVS) verification
4-Week Intensive Blueprint

8-Module RF IC Curriculum

A step-by-step masterclass taking you from RF transceiver architecture theory to tape-out-ready open-source silicon building blocks.

Program Leadership & Team

Meet the Stakeholders

Guiding the masterclass from theoretical foundations to physical open-source silicon tape-out.

Series Mentorship & Advisory

Dr. Vinayak Pachkawade
Series Guide & Mentor

Dr. Vinayak Pachkawade

Founder & Director, VPACHKAWADE Advisory • Ex-Univ. of Liège

Advanced non-executive advisor and researcher specializing in solid-state electronics, precision sensor systems, and micro-nanotechnology. Backed by Ph.D.-level expertise in Engineering and Technology Sciences from the University of Liège, Belgium, and author of Springer reference literature in 21st-century micro-nano systems.

Sumanto Kar
Technical MentorModule 1.1 Lead

Sumanto Kar

Project Research Engineer, FOSSEE, IIT Bombay • Open-Source EDA

Sumanto Kar completed his M.Tech in Industrial Engineering & Operations Research from IIT Bombay and B.E. in Electronics Engineering from Mumbai University. His interests lie in contributing to open-source EDA tools. He is actively involved with the FOSSEE project, contributing to the development, integration, documentation, and outreach of eSim, an open-source EDA platform used across universities in India. His work focuses on strengthening open technical ecosystems, enabling reproducible engineering workflows, and bridging the gap between academic research and community-driven software development.

Dr. Darshak Bhatt
Technical MentorModule 1.2 & 5 Lead

Dr. Darshak Bhatt

Associate Professor, Dept. of ECE, IIT Roorkee

Associate Professor in the Department of Electronics and Communication Engineering at Indian Institute of Technology Roorkee (IIT Roorkee). His specialized research domains encompass RF and Mixed-Signal IC design, high-frequency transceiver architectures, frequency synthesizers (PLLs), and analog/RF open-source EDA methodologies.

Souhadra Shrivastava
Course Curator

Souhadra Shrivastava

AI Engineer & IEEE-Published Researcher

Electronics & Telecom engineer, AI Engineer, and IEEE-published researcher working at the intersection of photonics and AI/ML.

Dr. Ramya H. R.
Faculty Advisor

Dr. Ramya H. R.

Associate Professor, Dept. of ETE, Ramaiah Institute of Technology (MSRIT)

Associate Professor in the Department of Electronics and Telecommunication Engineering at M.S. Ramaiah Institute of Technology with 21 years of experience. Her research interests span neural networks, fuzzy logic, machine learning, and Verilog design. She has published extensively in Scopus-indexed journals and conferences, with focus on medical image fusion, machine learning applications in healthcare, and signal processing. Dr. Ramya has established industry collaborations with Intel-Altera, Texas Instruments India, and Starcom Information Technology Limited to develop specialized labs and courses. She holds a design patent for "Multiband Antenna Tuning Device for 5G Networks" (Patent No. 450853-001).

Organising Committee

Priyanshu Trivedi
Lead Organiser

Priyanshu Trivedi

Chair, IEEE Sensors Council RIT-B • Founding Chair, IEEE TEMS RIT-B

Final-year Electronics and Telecommunication Engineering undergraduate at M.S. Ramaiah Institute of Technology, Bengaluru, working across embedded hardware, digital IC verification, and edge AI. Engineering experience spans designing electromechanical avionics systems for Edhitha UAS, building accelerated computer vision pipelines on embedded accelerators, and deploying agentic workflows. As Chair of IEEE Sensors Council RIT-B and Founding Chair of IEEE TEMS RIT-B, spearheads large-scale student initiatives, bridging academic study with open-source EDA workflows and physical silicon fabrication via the IEEE Open Silicon initiative.

Yashitha D
Course Manager

Yashitha D

Vice Secretary, IEEE Sensors Council RIT-B

ECE undergraduate with experience in FPGA design, Verilog HDL, RTL verification, and embedded systems. Gained industry experience at Bharat Electronics Limited (BEL) and Vaidisys Technologies, working on FPGA design, synthesis, and timing analysis. Hands-on experience in ALU design, ESP32-based battery management systems, and sensor-integrated wearable technology. Vice Secretary of the IEEE Sensors Council, contributing to technical events and student engagement.

Athar Sudhir Rao
Technical Lead

Athar Sudhir Rao

Mixed-Signal & RF Specialist • Ex-Intern, NAL

Final-year Electronics and Telecommunication Engineering student with hands-on experience across mixed-signal architectures, RF systems, and VLSI design. Previously interned at National Aerospace Laboratories, where they designed a 16-bit SAR ADC using discrete ICs, and developed wearable textile antennas for healthcare applications. Technical expertise spans digital design with Verilog, FPGA-based prototyping, PCB layout in KiCad, and electromagnetic modeling using Ansys HFSS.

Yug Bhimani
Webmaster & Technical Lead

Yug Bhimani

Full-Stack Developer & Platform Architect

Full-Stack Developer and Engineering Student leading the web platform architecture, digital infrastructure, and registration systems for the IEEE RF IC Design Series.

Dual-Tier IEEE Credentials

Tiered Certification & Silicon Capstone

Validate your engineering competence with verifiable IEEE credentials ranging from foundational attendance to physical silicon tape-out fabrication distinction.

Foundational TierIEEE Accredited

Certificate of Participation

Awarded to engineers and students who demonstrate dedication and maintain consistent attendance throughout the masterclass.

≥ 80% verified live session lecture & lab attendance
Active participation in Q&A, hands-on toolchain setup, and technical discussions
Official credential signed by IEEE Sensors Council & Section Leadership
Verification: Digital Certificate IDAll Registered Attendees
Capstone DistinctionFlagship

Certificate of Distinction

The ultimate credential for engineers who successfully complete and physically verify their RF IC capstone building block.

Design, simulate & layout a functional RF circuit (e.g., LNA, Mixer, VCO)
Pass automated DRC/LVS physical sign-off on 130nm Open-Source PDKs
Submit reproducible GitHub repository with SPICE testbenches & GDSII
Physical Tape-Out Opportunity

Series USP: Top validated student designs qualify for fabrication on open MPW shuttle runs (IHP / SkyWater open silicon)!

Sign-Off: Technical Committee & Industry LeadsTape-Out Eligible
Live Online Masterclass

Masterclass Schedule & Roadmap

Structured across 4 consecutive weekends with live online lectures, interactive hands-on lab sessions, and live tape-out office hours.

Every Saturday & Sunday • 7:30 PM – 9:30 PM IST (UTC+5:30)
Weekend 1Oct 24 - Oct 25, 2026

Architecture & Device Physics

Module 1 (Part 1.1 & 1.2) & Module 2

Instructors: Sumanto Kar (IIT-B), Dr. Darshak Bhatt (IIT-R), Abdur Rahman (IHP)

Interactive EDA Lab IncludedSession 1 & 2
Weekend 2Oct 31 - Nov 01, 2026

RF Circuits & S-Parameters

Module 3 (High-Frequency LNA) & Module 4 (Mixers)

Instructors: Industry Mentors & Technical Leads

Interactive EDA Lab IncludedSession 3 & 4
Weekend 3Nov 07 - Nov 08, 2026

Mask Layout & 3D EM Parasitics

Module 5 (Mask Layout) & Module 6 (openEMS Modeling)

Instructors: Dr. Darshak Bhatt & Yegappan Sethu

Interactive EDA Lab IncludedSession 5 & 6
Weekend 4Nov 14 - Nov 15, 2026

Tape-Out Pipeline & Sign-off

Module 7 (DRC/LVS) & Module 8 (MPW Submission)

Instructors: Krzysztof Herman (IHP), Dr. GS Javed (Intel), Rene Scholz

Interactive EDA Lab IncludedSession 7 & 8

Add Masterclass Sessions to Calendar

Never miss a live session. Sync all 8 weekend lectures and lab milestones directly to Google Calendar.

Add to Google Calendar
Free IEEE Micro-Specialization

Secure Your Participant Seat

Zero tuition fees. All toolchain access credentials, Zoom links, and student silicon tape-out slots are granted upon confirmed registration.

Personal & Contact Information

For critical tape-out coordination and lab access updates via SMS/WhatsApp.

Academic / Professional Profile
Profiles & Design Portfolios (Optional)

Check if you currently hold an active student or professional IEEE membership.

Official WhatsApp Community Group*

All live lecture links, EDA lab credentials, and physical tape-out announcements are shared exclusively here.

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By registering, you agree to receive session links and technical lab credentials via email and WhatsApp.