Master RF IC Design for 5G/6G on Open-Source Silicon
An intensive 8-Module Masterclass bridging high-frequency architectural theory, zero-cost FOSS EDA pipelines, and open-source MPW shuttle tape-outs with industry-standard Open-Source PDKs (OS PDKs). Top validated designs qualify for physical silicon tape-out fabrication!
From Schematic to Physical Silicon Tape-Out
Experience the complete semiconductor engineering lifecycle. Move past simulation theory into real-world Open-Source PDKs (OS PDKs) and automated MPW foundry manufacturing shuttles.
Foundry Open MPW Shuttles
Fabrication-ready flow targeting SkyWater 130nm CMOS and IHP 130nm BiCMOS open PDKs. Validated student team designs advance directly into physical silicon tape-out shuttles.
Zero-License FOSS Toolchain
Replace prohibitive enterprise EDA licenses ($150,000/seat/year) with production-grade open-source tools: Xschem, Ngspice, Qucs-S, and KLayout.
Real-Time DRC / LVS Sign-Off
Rigorous geometry Design Rule Checking (DRC) and Layout-Versus-Schematic (LVS) verification using Netgen and KLayout geometry engines.
IEEE Dual-Tier Credentials & Tape-Out Track
Earn institutional recognition endorsed by IEEE Sensors Council RIT-B & IEEE openSilicon. Outstanding designs qualify for the Flagship Silicon Capstone Tape-Out Distinction.
Proprietary vs. Open-Source Toolchain
Transitioning from prohibitive commercial enterprise licenses to production-grade FOSS EDA pipelines capable of tape-out on silicon foundries.
8-Module RF IC Curriculum
A step-by-step masterclass taking you from RF transceiver architecture theory to tape-out-ready open-source silicon building blocks.
Meet the Stakeholders
Guiding the masterclass from theoretical foundations to physical open-source silicon tape-out.
Series Mentorship & Advisory
Dr. Vinayak Pachkawade
Advisory and Technical Governance across STEM sectors, VPACHKAWADE
Advisor and non-executive independent director specializing in solid-state electronics, precision sensor systems, and micro-nanotechnology. Backed by Ph.D. in Engineering and Technology Sciences and long-standing international experience, his expertise and technical frameworks are published across high-impact global platforms.
Sumanto Kar
Project Research Engineer, FOSSEE, IIT Bombay • Open-Source EDA
Sumanto Kar completed his M.Tech in Industrial Engineering & Operations Research from IIT Bombay and B.E. in Electronics Engineering from Mumbai University. His interests lie in contributing to open-source EDA tools. He is actively involved with the FOSSEE project, contributing to the development, integration, documentation, and outreach of eSim, an open-source EDA platform used across universities in India. His work focuses on strengthening open technical ecosystems, enabling reproducible engineering workflows, and bridging the gap between academic research and community-driven software development.
Souhadra Shrivastava
SDE at Kodnest • Ex-Sarvm AI • IEEE-Published Researcher
Electronics & Telecommunication Engineering graduate from MS Ramaiah Institute of Technology, Bangalore, currently working as an SDE at Kodnest. Previously, he worked as an AI Product Manager at Sarvm AI, focusing on multilingual text-to-speech technologies. His research focuses on silicon photonics and EDA, where he builds AI-driven tools that use topology optimization to discover novel photonic chip structures, with GDSII export and fabrication constraints for foundry-ready layouts. He has also developed edge-AI hardware systems, including a real-time Braille-to-English converter on Jetson Orin, and built multi-agent AI systems at hackathons. Independently, he explores AI evaluations and agent memory, consults for educational institutions on AI adoption, and works as a freelance writer. Beyond technology and research, he is actively involved in social service, volunteering for animal welfare and participating in rescue missions during natural disasters. His commitment to helping vulnerable animals and communities reflects his sense of compassion, responsibility, and service. A former Chair of the IEEE Sensors Council RIT-B and recipient of the Best Outgoing EC Member Award 2025, he brings strong leadership, collaboration, and teamwork skills. He has also co-authored an IEEE publication on machine learning analysis of biological signal responses to music.
Dr. Ramya H. R.
Associate Professor, Dept. of ETE, Ramaiah Institute of Technology (MSRIT)
Associate Professor in the Department of Electronics and Telecommunication Engineering at M.S. Ramaiah Institute of Technology with 21 years of experience. Her research interests span neural networks, fuzzy logic, machine learning, and Verilog design. She has published extensively in Scopus-indexed journals and conferences, with focus on medical image fusion, machine learning applications in healthcare, and signal processing. Dr. Ramya has established industry collaborations with Altera, Texas Instruments India, and Starcom Information Technology Limited to develop specialized labs and courses. She holds a design patent for "Multiband Antenna Tuning Device for 5G Networks" (Patent No. 450853-001).
Resource Persons of the Series
Sumanto Kar
Project Research Engineer, FOSSEE, IIT Bombay • Open-Source EDA
Sumanto Kar completed his M.Tech in Industrial Engineering & Operations Research from IIT Bombay and B.E. in Electronics Engineering from Mumbai University. His interests lie in contributing to open-source EDA tools. He is actively involved with the FOSSEE project, contributing to the development, integration, documentation, and outreach of eSim, an open-source EDA platform used across universities in India. His work focuses on strengthening open technical ecosystems, enabling reproducible engineering workflows, and bridging the gap between academic research and community-driven software development.
Dr. Darshak Bhatt
Associate Professor, Dept. of ECE, IIT Roorkee
Associate Professor in the Department of Electronics and Communication Engineering at Indian Institute of Technology Roorkee (IIT Roorkee). His specialized research domains encompass RF and Mixed-Signal IC design, high-frequency transceiver architectures, frequency synthesizers (PLLs), and analog/RF open-source EDA methodologies.
Organising Committee
Priyanshu Trivedi
Chair, IEEE Sensors Council RIT-B • Founding Chair, IEEE TEMS RIT-B
Final-year Electronics and Telecommunication Engineering undergraduate at M.S. Ramaiah Institute of Technology, Bengaluru, working across embedded hardware, digital IC verification, and edge AI. Engineering experience spans designing electromechanical avionics systems for Edhitha UAS, building accelerated computer vision pipelines on embedded accelerators, and deploying agentic workflows. As Chair of IEEE Sensors Council RIT-B and Founding Chair of IEEE TEMS RIT-B, spearheads large-scale student initiatives, bridging academic study with open-source EDA workflows and physical silicon fabrication via the IEEE Open Silicon initiative.
Yashitha D
Vice Secretary, IEEE Sensors Council RIT-B
ECE undergraduate with experience in FPGA design, Verilog HDL, RTL verification, and embedded systems. Gained industry experience at Bharat Electronics Limited (BEL) and Vaidisys Technologies, working on FPGA design, synthesis, and timing analysis. Hands-on experience in ALU design, ESP32-based battery management systems, and sensor-integrated wearable technology. Vice Secretary of the IEEE Sensors Council, contributing to technical events and student engagement.
Athar Sudhir Rao
Mixed-Signal & RF Specialist • Ex-Intern, NAL
Final-year Electronics and Telecommunication Engineering student with hands-on experience across mixed-signal architectures, RF systems, and VLSI design. Previously interned at National Aerospace Laboratories, where they designed a 16-bit SAR ADC using discrete ICs, and developed wearable textile antennas for healthcare applications. Technical expertise spans digital design with Verilog, FPGA-based prototyping, PCB layout in KiCad, and electromagnetic modeling using Ansys HFSS.
Tiered Certification & Silicon Capstone
Validate your engineering competence with verifiable IEEE credentials ranging from foundational attendance to physical silicon tape-out fabrication distinction.
Masterclass Schedule & Roadmap
Structured across 4 consecutive weekends with live online lectures, interactive hands-on lab sessions, and live tape-out office hours.
Architecture & Device Physics
Module 1 (Part 1.1 & 1.2) & Module 2
Instructors: Sumanto Kar (IIT-B), Dr. Darshak Bhatt (IIT-R), Abdur Rahman (IHP)
RF Circuits & S-Parameters
Module 3 (High-Frequency LNA) & Module 4 (Mixers)
Instructors: Industry Mentors & Technical Leads
Mask Layout & 3D EM Parasitics
Module 5 (Mask Layout) & Module 6 (openEMS Modeling)
Instructors: Dr. Darshak Bhatt & Yegappan Sethu
Tape-Out Pipeline & Sign-off
Module 7 (DRC/LVS) & Module 8 (MPW Submission)
Instructors: Krzysztof Herman (IHP) & Rene Scholz
Add Masterclass Sessions to Calendar
Never miss a live session. Sync all 8 weekend lectures and lab milestones directly to Google Calendar.
Secure Your Participant Seat
Zero tuition fees. All toolchain access credentials, Zoom links, and student silicon tape-out slots are granted upon confirmed registration.